Product · Compression IP core

BioRLE-1

Biomedical signal compression IP for cardiac monitors. Open algorithm core under Apache 2.0, licensed integration layer, validated and ready for tape-out.

Category: Compression IP core Domain: ECG / biosignals Status: Tape-out ready

What it is

A dedicated compression block that sits between acquisition and everything downstream.

BioRLE-1 takes the digitised output of the analogue front end and emits a compressed frame before the data ever reaches memory or the radio. Everything downstream — storage, buffering, transmission, cloud ingest — handles a smaller payload as a result.

Because it is a hardware block rather than firmware, the compression happens without spending host MCU cycles, and the power cost is bounded and predictable rather than dependent on what else the processor is doing.

Where it fits: AFE → ADC → BioRLE-1 → memory / MCU / radio. It is deliberately narrow: one job, done in a small, verifiable amount of logic.

Signal chainsimplified
// acquisition electrodes → AFE → ADC | v [ BioRLE-1 compression core ] | v // downstream, now smaller flash · MCU · BLE / LTE-M · cloud // reconstruction host / cloud → decoder → waveform

Specifications

Technical summary

Figures marked TBD are confirmed per engagement against your signal database, target process and interface requirements.

ParameterValueNotes
FunctionLossless biosignal compressionFirst-order delta + RLE
Target signalECG / EEGFrom TI ADS1292R front end
Compression ratio2–4× typicalMIT-BIH Arrhythmia, records 100–109
ReconstructionLosslessSample for sample, zero error
Input resolution16 bits per sampleDelta saturated to 8 bits with flag
Sample rateUp to 8 kSPSPer channel
Channels2 (CH1 / CH2)Selectable, one at a time
Input interfaceSPI mode 172-bit frame, up to 4 MHz
Output interfaceUART 921,600 bps8N1, (value, count) pairs
System clock25 MHzSingle domain
Area852 standard cells9,892 µm² cell area
Process nodeSkyWater 130 nmsky130A
Timing closureSetup and hold metAt 25 MHz, no violations
PowerCharacterisation pendingRequires measurement on silicon
LanguageVerilogSynthesisable RTL
Verification31/31 unit · 7/7 gate-levelcocotb
Core licenceApache 2.0Reference implementation
StatusValidated · tape-out readyTiny Tapeout precheck passed
Scope of these figures: they correspond to the first hardened implementation of the core. Commercial product figures are confirmed per engagement, against your signal database and your target process.

What you receive

Deliverables

RTL

Design files

Synthesisable RTL for the encoder, the matching decoder and the configuration registers.

TB

Verification collateral

Testbench, reference vectors and results you can re-run inside your own flow.

DOC

Integration guide

Interface description, register map, timing expectations and integration checklist.

MDL

Software model

A bit-accurate model to validate the reconstruction path in your own software stack.

EVL

Evaluation package

Run the compression against your own recordings before committing to a licence.

SUP

Engineering support

Direct access to the design team through integration, synthesis and bring-up.

Ready to see it against your data?

We will scope an evaluation around your signals, your interfaces and your power budget.