Product · Compression IP core
BioRLE-1
Biomedical signal compression IP for cardiac monitors. Open algorithm core under Apache 2.0, validated and ready for tape-out. The licensed integration layer is in development.
What it is
A dedicated compression block that sits between acquisition and everything downstream.
BioRLE-1 takes the digitised output of the analogue front end and emits a compressed frame before the data ever reaches memory or the radio. Everything downstream — storage, buffering, transmission, cloud ingest — handles a smaller payload as a result.
Because it is a hardware block rather than firmware, the compression happens without spending host MCU cycles, and the power cost is bounded and predictable rather than dependent on what else the processor is doing.
Where it fits: AFE → ADC → BioRLE-1 → memory / MCU / radio. It is deliberately narrow: one job, done in a small, verifiable amount of logic.
Specifications
Technical summary
Figures marked TBD are confirmed per engagement against your signal database, target process and interface requirements.
| Parameter | Value | Notes |
|---|---|---|
| Function | Lossless biosignal compression | First-order delta + RLE |
| Target signal | ECG / EEG | From TI ADS1292R front end |
| Compression ratio | 2–4× typical | MIT-BIH Arrhythmia, records 100–109 |
| Reconstruction | Lossless | Sample for sample, zero error |
| Input resolution | 16 bits per sample | Delta saturated to 8 bits with flag |
| Sample rate | Up to 8 kSPS | Per channel |
| Channels | 2 (CH1 / CH2) | Selectable, one at a time |
| Input interface | SPI mode 1 | 72-bit frame, up to 4 MHz |
| Output interface | UART 921,600 bps | 8N1, (value, count) pairs |
| System clock | 25 MHz | Single domain |
| Area | 852 standard cells | 9,892 µm² cell area |
| Process node | SkyWater 130 nm | sky130A |
| Timing closure | Setup and hold met | At 25 MHz, no violations |
| Power | Characterisation pending | Requires measurement on silicon |
| Language | Verilog | Synthesisable RTL |
| Verification | 31/31 unit · 7/7 gate-level | cocotb |
| Core licence | Apache 2.0 | Reference implementation |
| Status | Validated · tape-out ready | Tiny Tapeout precheck passed |
Transparency
Known limitations
None of the following is solved yet. We would rather say it than have someone find it out halfway through an integration.
Tied to one specific front end
The input interface is built around the 72-bit SPI frame of the TI ADS1292R. Adapting it to another converter is engineering work, not a configuration parameter. Portability across front ends is roadmap, not a current capability.
The integration layer does not exist yet
What is built and validated is the algorithm core. The hardened RTL with standard bus interfaces, the register map and the supporting collateral are in development.
Power is not characterised
There is no power figure because there is no silicon to measure it on. Any number we gave today would be a synthesis estimate, not a measurement.
Bounded validation
The 2–4× compression ratio comes from records 100–109 of the MIT-BIH Arrhythmia database. That is a public, recognised baseline, but it is no substitute for an evaluation against your own signals.
What you receive
Intended deliverables
What exists today is the design files of the core and its verification collateral. The rest belongs to the package that will ship with the integration layer.
Design files
Synthesisable RTL for the encoder, the matching decoder and the configuration registers.
Verification collateral
Testbench, reference vectors and results you can re-run inside your own flow.
Integration guide
Interface description, register map, timing expectations and integration checklist.
Software model
A bit-accurate model to validate the reconstruction path in your own software stack.
Evaluation package
Run the compression against your own recordings before committing to a licence.
Engineering support
Direct access to the design team through integration, synthesis and bring-up.
Ready to see it against your data?
We will scope an evaluation around your signals, your interfaces and your power budget.